1. Field of the Invention
The invention relates to a self-aligned process for fabricating improved high performance bipolar transistors.
2. Discussion of the Related Art
Numerous integrated circuit devices, structures and techniques of fabricating the same, are known in the art.
The present trend in semiconductor technology is toward large scale integration of devices with very high speed and low power dissipation. To achieve this goal, it is essential that the devices be made as small as possible and that the parasitic capacitance be reduced to a small value. These high performance devices can be made by (a) making the vertical junction structure shallow, (b) reducing the horizontal geometry and (c) achieving complete dielectric isolation.
Shallow-junction device profile can be achieved with ion-implantation of dopant species. Ion-implantation technique permits precise control of the impurity dose and depth of penetration into the semiconductor. Unlike the conventional thermal diffusion process, ion-implantation is not a high temperature process. Thus, by using lithographic resist or metal maskings, multiple impurity introduction operations can be achieved without resort to high temperatures. Exposure to high temperature, as in the diffusion process, disperses the impurities previously introduced. For the implanted device, a designed thermal cycle is used to activate and diffuse the various dopant species to the desired junction depth and profile.
Device horizontal geometry depends to a large extent on the lithographic tools available. Within a given constraint, however, the use of a self-aligned process can greatly reduce the device horizontal dimension. By implementation of the dielectric isolation scheme such as Recessed Oxide Isolation (ROI) or Deep Dielectric Isolation (DDI) the successive fabrication steps can be done in a self-alignment fashion. In addition to reduction of device horizontal geometry, dielectric isolation also eliminates the sidewalls of the device doping regions and thus further reduces the device parasitic capacitances. A problem associated with the ROI is the formation of a "bird's beak" and "bird's head" structure at the lateral edges of the recessed oxide. The "bird's beak" structure prevents the device junction sidewalls to fully butt against the dielectric isolation and thus imposes the need for wider tolerance of device lateral dimension. Deep dielectric isolation DDI, however, avoids the above mentioned ROI problem. Unlike the "bird's beak" structure in ROI, sidewalls of the DDI structure are nearly vertical. Also, the surface of the DDI regions and the silicon where device regions ar to be formed is coplanar. Reference is made to U.S. Pat. No. 4,104,086 entitled "Method For Forming Isolated Regions of Silicon Utilizing Reactive Ion Etching" granted Aug. 1, 1978 to J. A. Bondur et al., and U.S. Pat. No. 4,139,442 entitled "Reactive Ion Etching Method For Producing Deep Dielectric Isolation in Silicon" granted Feb. 13, 1979 to J. A. Bondur et al., respectively of common assignee herewith.
For the very small bipolar transistor, as for example, submicron size transistor, the base area and hence the collector-base junction capacitance is the most significant performance parameter. The active base area in the bipolar transistor is the region below the emitter. The base region which surrounds the emitter is the inactive base. On conventional transistors, the metal to base contact is formed directly above the inactive base region. The transistor base area that is needed to accommodate the emitter and base contacts is considerably larger than the active base region.
To reduce the transistor base area, a process using polysilicon for making contact to the base is described in U.S. Pat. No. 4,160,991 entitled "High Performance Bipolar Device and Method for Making Same" granted Jul. 10, 1979 to N. G. Anantha et al. and of common assignee herewith. The Anantha et al patent discloses a method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing. The small emitter-base spacing reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subsollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is then removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base region.
In Anantha et al., the heavily doped polysilicon is used to make contact to the transistor base. The metal to polysilicon contact is formed outside the base region and over the oxide isolation area. The emitter opening process described in Anantha et al., however, is not a self-aligned process. Therefore, transistor base area of the Anantha et al. device must be large enough to allow polysilicon to make low resistance contact to the base and also provide a sufficient leeway for the misregistration of the emitter contact to the doped region. Since the base area and hence the base-collector junction capacitance is a very important parameter in the performance of a very fast device, it is necessary to reduce this area to the minimum possible value.
In the article "A 30-ps Si Bipolar IC Using Super Self-Aligned Process Technology" by Konaka et al. (IEEE Transactions on Electronic Devices, Vol. ED-33, No. 4, April 1986, pages 526-531) a transistor fabrication process is described. In the fabrication of an n-p-n transistor according to Konaka et al., the emitter is self-aligned with respect to the base contact and the base contact is self-aligned with respect to the base, and therefore only one photomasking operation is required in order to form the transistor. In this method, a silicon nitride layer is formed over the region of the substrate in which the transistor is to be formed, and a layer of polysilicon is deposited over the silicon nitride layer. The polysilicon over the area corresponding to the emitter and base of the transistor is removed by a photomasking and etching operation, exposing the silicon nitride layer, and a surface layer of the polysilicon that remains is oxidized. The silicon nitride exposed by removal of polysilicon is removed by etching, and during the etching silicon nitride is removed from under the polysilicon, leaving a cavity. Polysilicon is depositied into the cavity providing a connection between the first deposit of polysilicon and the region that will be the base of the transistor. This method is subject to the disadvantage that it is difficult to control the side etching operation whereby the silicon nitride underneath the polysilicon is removed. Moreover, it is possible that voids will be formed when the polysilicon is deposited into the cavity formed by the side etching operation, so that reliability of connections between the first deposit of polysilicon and the base can not be ensured. In addition, while the fabrication process of Konaka et al. provides a self-aligned process using only one mask, it is further disadvantageous in high volume manufacturing of transistor devices. That is, the extra process steps, including the second polysilicon deposition step, increase manufacturing complexity and cost. In addition, the additional etching steps required by Konaka et al. introduce the increased possibility for defects in the resultant structure.
Another self-alignment technique for fabricating a bipolar transistor is disclosed in the article "Fabrication Process and Device Characteristics of Sidewall Base Contact Structure Transistor Using Two-Step Oxidation of Sidewall Surface" by Washio et al., IEEE Transactions on Electron Devices, Vol. 35, No. 10, October 1988, pages 1596-1600. The technique disclosed in Washio et al. includes two-step oxidation of a sidewall surface to achieve a desired SiO.sub.2 sidewall thickness. Optimization of silicon nitride thicknesses is also required. The two-step oxidation process is necessary to prevent extension of a "bird's beak" to the first sidewall SiO.sub.2 so that the sidewall window can be selectively opened and to prevent the generation of defects. In addition, due to the bird's beak of the second oxidation, it is difficult to control the size of the "graft-base" sidewall contact between the poly-crystalline and mono-crystalline silicon base. Such a technique involving repeated or added steps is undesireable and not well suited for a high volume manufacturing environment.
In yet another article, entitled "SDX: A Novel Self-Aligned Technique and Its Application to High-Speed Bipolar LSI's" by Yamamoto et al., IEEE Transactions on Electron Devices, Vol. 35, No. 10, October 1988, pages 1601-1608, a self-aligned fabrication process is disclosed. The SDX process comprises four subprocesses which include: boron doping into a substrate, depositing undoped polysilicon on the substrate, thermally diffusing the boron impurity from the substrate into the polysilicon; and selectively etching the polysilicon, whereby the low boron-doped polysilicon is etched but the highly boron-doped polysilicon is not. While the SDX process provides for self-alignment of an isolation and transistor pattern, the process disadvantageously requires numerous steps which add complexity to the transistor fabrication process. In addition, the sloping opening makes it difficult to form the additional base-emitter sidewall. The added complexity is undesireable in a high volume manufacturing environment.
In U.S. Pat. No. 4,994,400 entitled "Method of Fabricating a Semiconductor Device Using a Tri-layer Structure and Conductive Sidewalls" granted to Yamaguchi et al. and issued Feb. 19, 1991, a tri-layer structure is disclosed. The tri-layer structure with conductive sidewalls is disadvantageously susceptible to formation of the above-mentioned "bird's beak". That is, formation of the conductive polysilicon sidewalls followed by deposition of the SiO.sub.2 layer make the structure highly susceptible to the formation of "bird's beak" and the disadvantages associated therewith. The procedure requires triple reactive ion etching of the active base, making it susceptible to defects. Also, the sloping nature of the conducting sidewall makes it difficult to form a second insulating sidewall, giving increased possibility of base-emitter short circuits. Furthermore, the method of Yamaguchi et al. involves numerous fabrication steps which add complexity to the manufacturing process. Such complexity is disadvantageous and undesireable in high volume manufacturing of bipolar devices.
It is thus desireable to provide a self-aligned emitter to polysilicon base process which is unsusceptible to disadvantages associated with the formation of "bird's beak". It is further desireable to provide a bipolar transistor fabrication process which is simple to implement and advantageous for use in high volume manufacturing of bipolar transistor devices.